Design of Level Shifter for Multiple Supply Voltage SOC

Level shifter is an interfacing device playing a wide application in System On Chip (SOC) design. Modern SOC utilize Multi Supply Voltage Design (MSVD) because of their low static and dynamic power consumption. When a high voltage supplied cell of SOC is driven by a low voltage supplied cell then their occur error due to inability of low signal to drive a high voltage cell. For interfacing these two different voltage driven cells a level shifter is necessary between them. Since Multi Supply Voltage Design is adopted to reduce power consumption the added interfacing device should not degrade its value. In this paper I compared a variety of existing level shifter upconverting near/sub threshold level to super threshold levels in terms of power and delay. From the comparison I came to know DCVS level shifter be the best among all other level shifter circuit. Thus I proposed DCVS with NMOS diode current limiter level shifter to provide improved conversion range with less power consumption and reduced delay. CADENCE Virtuoso 180 nm CMOS technology is utilized for performing simulation, layout editing, RC extraction and post layout simulation.